This application claims priority of Korean Patent Application No. 10-2004-0026247, filed on Apr. 16, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor package having a lead frame with multiple rows of leads arranged about a semiconductor chip of the semiconductor package.
2. Description of the Related Art
As semiconductor chips become more highly integrated, the number of input/output terminals for electrically interconnecting a semiconductor chip to an external PCB needs to be greatly increased. Accordingly, continuing research efforts have been made to develop a semiconductor package having a great number of leads, for example, at least two rows of leads arranged around the semiconductor chip in which the leads of each row are separately connected to a semiconductor chip and an external substrate.
FIG. 1 is a flowchart illustrating a conventional method of manufacturing a semiconductor package. A base lead frame is first fabricated to form the desired shape of the lead frame (that is, operation S10). For example, a plurality of small apertures are formed between leads of the lead frame by stamping or etching while also forming structural elements such as dam-bars, rails or outer frames, or the like. The lead frame is often pre-plated, for example, with Ni, Pd, and Au plating layers (operation S20). Thus, a subsequent solder plating process for applying lead-solder on the lead frame can be omitted by this pre-plating process in which the lead frame is coated with the plating layers having an excellent solder-wettability before performing a semiconductor molding process.
Thereafter, an adhesive tape is attached to a surface of the lead frame (operation S30). By attaching the adhesive tape to at least one surface (e.g., a rear surface) of the lead frame, the lead frame can be kept in a planar shape in a subsequent semiconductor molding process, and a mold flashing phenomenon can be reduced, which is a problem such that molding material flows on the surface of the lead frame.
Next, as a semiconductor packaging process, the semiconductor chip is attached to a die pad of the lead frame, and plural terminals of the semiconductor chip are connected to the multiple rows of leads with wires, and the semiconductor chip, wires, and internal leads are then sealed with insulators such as thermosetting plastics (operation S40). Thereafter, the adhesive tape is removed from the lead frame (operation S50).
In an effort to provide semiconductor packages with a great number of leads, a lead frame with multiple rows of leads arranged around the die pad has been suggested. In order to make such a semiconductor package, each of the leads formed unitarily in operation S10 is now subjected to a separation or individualization process (operation S60). This is a process in which leads of neighboring rows are separated (individualized) by removing the lead portions between the leads of neighboring rows. This process of individualizing leads of neighboring rows has been suggested to be performed after the semiconductor packaging (i.e., molding) process. This individualization process (as a post packaging process) is difficult to perform and requires additional manufacturing costs. In addition, coherence in the bonding surfaces between the molding material and the lead frame may be damaged because this process is performed as a post molding process.